The news keeps saying “TSMC’s 2nm goes into production” and “Intel pushes into GAA.” It sounds impressive — but what actually is 2nm? Is it really as small as 2 nanometers? And what on earth is GAA?
This piece spells out the advanced process. First we’ll defuse “process node,” a term that’s easy to misread, then look at how the transistor evolved from planar to GAA, where 2nm stands now, what the next move is, and why the most advanced processes are more expensive and harder. This is the deep-dive upgrade of the Foundry gate.
What Is a Process Node?
Let’s first defuse a common misconception: 3nm and 2nm do not mean that some component inside the chip is really only 3 or 2 nanometers wide.
A process node is now mainly a commercial name for a “technology generation.” It represents progress across a whole bundle of metrics: better performance, lower power, transistors packed more densely, newer design rules. In the early days the node number still roughly corresponded to some dimension of the transistor, but once we passed below 10nm that correspondence broke apart long ago, and the numbers became more like codenames each company uses to mark a generation (which is also why names like A16 and A14, using the “angstrom” as the unit, later appeared).
So when you see 2nm, just read it as “one more denser, more power-efficient generation,” and don’t fixate on the number itself.
Core-Data Snapshot
The numbers below help you grasp where the advanced process stands. The timing and specs are mostly each company’s targets or estimates, so read them for order of magnitude.
| Topic | Data | Timing / Nature |
|---|---|---|
| TSMC 2nm (N2) | Entered high-volume production in Q4 2025, ramping fast in 2026 | TSMC official |
| N2 performance / power vs. N3E | About 10-15% faster at the same power, or 25-30% lower power at the same performance, with over 15% higher density | TSMC roadmap target |
| Samsung 2nm (SF2) | First gen in mass production from Q4 2025; second gen planned for H2 2026 | Samsung official |
| Intel 18A | Entered production ramp in 2025, Panther Lake shipping by year-end (RibbonFET + PowerVia) | Intel official |
| TSMC A16 (with backside power) | N2P / A16 planned for volume production in H2 2026 | TSMC official schedule |
How the Transistor Evolved: Planar → FinFET → GAA
The root of a chip getting stronger is the transistor — the tiny switch that controls whether current flows or stops — being made smaller and smaller and more power-efficient. But the smaller it gets, the easier it “leaks,” so the transistor’s structure has evolved along with it.
Planar transistor: the earliest structure, where the gate controls the current only from the top. Past a certain point of shrinking, control isn’t strong enough and leakage gets severe. FinFET: stands the channel up into a “fin” so the gate wraps around three sides, greatly boosting control — it carried the generations from 16nm down to 5nm. GAA (Gate-All-Around): uses stacked horizontal nanosheets (like several very thin horizontal channels) as the channel, so the gate fully wraps it on all four sides — less leakage, more transistors in the same area. Samsung adopted GAA first at 3nm, while TSMC introduced it at 2nm.
Here’s an analogy: a planar transistor is like pressing down on a hose with just one hand from above, FinFET is like cupping three sides with your palm, and GAA is like wrapping a full ring around the hose — control is naturally steadier. Looking further out, the industry is still researching CFET, which stacks transistors on top of one another, but that’s still at the lab stage.
2nm and GAA: Where It Stands Now
2nm is the focal race of 2025 through 2026, and the three big players are at different stages.
TSMC’s N2 entered high-volume production in Q4 2025 and is ramping fast in 2026 — it’s TSMC’s first GAA process. The official target is, versus the previous N3E, about 10-15% faster at the same power, or 25-30% lower power at the same performance, with density up over 15%. Samsung’s first-gen 2nm has also begun mass production, with the second generation planned for H2 2026. Intel uses 18A (with RibbonFET, also a form of GAA), which entered production in 2025 and is ramping toward volume, with the first batch of Panther Lake shipping at the end of 2025.
Worth noting: the performance figures each company publishes are mostly roadmap targets. The real deciders are actual yield, customer adoption, and production scale — and those are still in progress.
Backside Power: The Next Move After 2nm
Once transistors are packed to a certain point, power delivery becomes a bottleneck too.
In a traditional chip, the power lines and signal lines are all crammed above the transistors, getting more congested and interfering with each other the more advanced the chip is. The idea of backside power is to move the metal network handling power delivery to the back of the chip, leaving more room on the front for signal lines — reducing voltage loss and improving performance and density. TSMC’s A16 uses “Super Power Rail,” planned for the A16 generation after 2nm; Intel’s PowerVia has already been introduced together with 18A. This is one of the key moves keeping scaling alive.
Why the Most Advanced Processes Are So Expensive and So Hard
The advanced process is a game for a handful of players, because it consumes three hard resources at once.
First, equipment: the most advanced processes need ASML’s extreme ultraviolet (EUV) lithography machines, and the next step requires even pricier High-NA EUV (a new generation of EUV with higher numerical aperture and stronger resolution), each costing hundreds of millions of dollars — and only ASML can build them (for details, see the ASML gate). Second, yield: a new structure and new process take a very long time to push the good-die rate up, and insufficient yield is just burning money. Third, the design ecosystem: the more advanced the process, the more complex the supporting design tools, silicon IP, and design rules — in 2025 alone TSMC provided tens of thousands of design files and silicon IP. Stack all three, and the barrier rises so high that only a handful of companies in the world can afford to play.
Taiwan’s Role
Taiwan’s core role is as the “volume-production and yield platform for the most advanced logic processes.” TSMC’s 3nm already makes up roughly a quarter of its wafer revenue, and 2nm was the first to enter high-volume production at the end of 2025 — meaning the world’s most cutting-edge process production base is still in Taiwan.
This echoes the concentration phenomenon described in the Foundry gate: ramping a new process requires R&D, equipment, and talent to be tightly co-located, and TSMC also puts its most advanced processes in Taiwan first. The stable mass production of advanced processes directly affects the upstream capability of the AI-compute supply chain.
Key Takeaways for This Gate
After looking at the advanced process, first remember three points: a process node is the name of a technology generation, not a real line width; transistor structure has gone from planar to FinFET to today’s GAA; and 2nm is the current focal race, with backside power as the next move.
Process scaling keeps getting more expensive and harder, but it remains one of the fundamental sources of AI-chip performance. The stable mass production of advanced processes affects the upstream capability of the AI-compute supply chain, and that position is still centered on Taiwan today.
To see the foundry model and the industry landscape, go back to Foundry; to see the equipment that is the lifeline of the process, see ASML; to see how packaging takes the baton, see Advanced Packaging; to look back at all eight gates of the chain, head back to the supply-chain overview.