Talk about AI hardware and everyone watches the GPU, HBM, and CoWoS. But one gate keeps getting named more and more: when an AI data center packs in tens of thousands of GPUs, how do those chips exchange data with each other in a way that’s both fast enough and power-efficient enough? The answer increasingly points to one word: silicon photonics.
This piece lays out silicon photonics and optical interconnect all at once. First what it is and why AI can’t do without it, then how the hottest topic — CPO co-packaged optics — saves power, where it stands today, and Taiwan’s place in this chain. This is the deep-dive version of Gate 5 in The AI Hardware Supply Chain, End to End.
What Is Silicon Photonics? One Sentence to Make It Clear
The core of silicon photonics is building the components that carry light into a silicon chip or package.
Inside a chip, data is an electrical signal. What silicon photonics does is convert that electrical signal into an optical signal, send it out over fiber or an on-chip optical path, then convert it back to an electrical signal for processing at the other end. Remember it in one line: silicon photonics is the technology for moving data with light. The GPU still computes with electricity; silicon photonics handles shuttling the results between chips at high speed.
Why go to all this trouble to bring light into the chip? Because traditionally, “light” only happened inside an external optical module — the electrical signal had to travel a stretch across the circuit board before being converted to light. AI’s data volume is so large that even this stretch becomes a burden, so the industry wants to move the point of optical conversion as close to the chip as possible.
Why AI Clusters Increasingly Need Optical Interconnect
Picture an AI data center as a giant sports team. The GPUs are the players, and optical interconnect is the passing routes between them. The more players there are and the more spread out they stand, the higher the demands on the distance and speed of each pass.
When training a large model, tens of thousands of GPUs constantly exchange data, and the switch isn’t necessarily in the same rack. As the distance stretches, traditional copper struggles: signals attenuate and distort, while power draw and heat shoot up. Switching to fiber transmission keeps speed high over longer distances while using less power. Speeds keep climbing too, from 400G to 800G to 1.6T.
That’s why “optical interconnect” carries more and more weight in AI infrastructure. One caveat: very short-distance connections still use copper cabling — optical mainly tackles the bottleneck of higher bandwidth, longer distance, and crossing racks first. The more concentrated the compute, the more the data pipe determines whether the whole data center can run at all.
Core-Data Snapshot
The following numbers help you grasp where optical interconnect stands today. Industry penetration and share figures are mostly estimates from research firms, so read them for trend rather than the decimal point.
| Topic | Data | Time / Nature |
|---|---|---|
| Share of 800G+ optical module shipments | Rising from about 19.5% in 2024 to over 60% in 2026 | 2024-2026, TrendForce estimate |
| 1.6T optical modules | Gradually entering volume ramp in 2026, not yet a full replacement for 800G | 2026 |
| CPO power per interface | Traditional pluggable optical modules commonly about 30 watts; CPO as low as about 9 watts | Nvidia figures |
| CPO electrical loss | Traditional about 22 dB, CPO about 4 dB | Nvidia figures |
| CPO penetration in AI data-center optical modules | About 0.5% in 2026, estimated to reach about 35% by 2030 | 2026-2030E, TrendForce estimate |
CPO Co-Packaged Optics: Moving the Optical Engine Right Next to the Chip
For this optical-interconnect gate, the hottest keyword in 2026 is CPO.
CPO stands for co-packaged optics. What it does is place the “optical engine” directly beside the switch chip or accelerator in the same package, so the electrical signal doesn’t have to travel a long way across the circuit board before being converted to light. The closer the point of optical conversion is to the chip, the smaller the electrical loss to fight, and the more power saved.
How much does it save? By Nvidia’s published figures, a traditional pluggable optical module commonly runs about 30 watts per interface with electrical loss of up to about 22 dB (here decibels track signal loss — the lower the number, the less the compensating circuitry and power needed). Switch to CPO and that drops to about 9 watts and about 4 dB. In its technical post, Nvidia marks the corresponding Spectrum-X Photonics efficiency gain at about 3.5x (the product page uses 5x as a marketing framing). In an AI cluster with tens of thousands of ports, that power saving gets magnified enormously — it’s like reclaiming power that would have gone to heat and giving it to more GPUs.
Products are starting to land too. Nvidia has put two silicon-photonics switches, Quantum-X and Spectrum-X Photonics, into its product line (single-unit switch capacity reaching the hundreds-of-Tb-per-second class), and Broadcom has announced its Tomahawk 6-Davisson CPO switch built on TSMC’s platform, shipping samples to early customers. All of this has pushed CPO from the lab to the doorstep of commercial use.
Where It Stands Today: First Year of Adoption, Not a Full Boom
Here’s a pragmatic call: 2026 is the “first year of adoption” for CPO and silicon photonics, not yet a wholesale replacement.
High-speed optical modules currently run mostly on 800G, with 1.6T ramping into volume in 2026. As hot as CPO’s buzz is, research firms estimate its penetration in AI data-center optical modules at only about 0.5% in 2026, likely not climbing to the low thirties percent until 2030. In other words, CPO is a sure direction, but mass adoption takes time, and the technical bar and yield are still being cleared.
Another signal worth noting is standardization. In early 2026, AMD, Broadcom, and Nvidia, together with Microsoft, Meta, OpenAI, and others, formed an optical-interconnect standards alliance (OCI MSA) to set specs for short-distance optical links inside the AI rack: starting at 200 Gb/s per direction, the next generation at 800 Gb/s per fiber, with a roadmap reaching 3.2 Tb/s and beyond. So many giants willing to set a standard together signals that optical interconnect is now treated as a long-term backbone of AI infrastructure.
Taiwan’s Role at This Gate
At this optical-interconnect gate, Taiwan’s involvement runs deeper than many assume.
The most watched is TSMC’s silicon-photonics integration platform COUPE, which integrates the silicon-photonics chip and the electronic-control chip into a single optical engine that can be co-packaged with a high-performance compute chip; in 2025 it achieved 200 Gb/s per second with customers, with related solutions targeting mass production in 2026. Beyond foundry and platform, Taiwanese firms are also spread across optical-module assembly and testing, passive optical components (connectors, lenses, and other parts that don’t actively emit light), and optoelectronic components, and they appear on Nvidia’s silicon-photonics ecosystem partner roster.
So at this optical-interconnect gate, Taiwan stands both at the most upstream silicon-photonics platform and in the mid-to-downstream modules and components. For a fuller look at which links and which companies are involved, Penchan will break it open later in a standalone optical-communications piece. This is just an industry map, with no investment judgment on any individual stock.
Key Takeaways for This Gate
After looking at optical interconnect, a few things are worth remembering.
Silicon photonics is the technology for moving data with light. As AI clusters grow ever larger and copper grows ever more strained, it shifts from a supporting role to key infrastructure. The hottest topic, CPO, hugs the optical engine right next to the chip, trading dramatic power savings for higher bandwidth density.
But take a pragmatic view of the timeline: in 2026, 800G is still mainstream and 1.6T is ramping, while CPO penetration is still very low — an early-adoption phase. Nvidia, TSMC, and Broadcom have already pushed products and platforms to the doorstep of commercial use, and with the giants forming a standards alliance, the direction is clear; what’s left is the pace of adoption.
To read on about other stories that rely on advanced packaging to bond components together, see What Is CoWoS and What Is HBM; to see how all eight gates of the chain string together, head back to the supply-chain overview.