Every time AI chip shortages come up, alongside TSMC’s CoWoS packaging the other bottleneck that gets named is HBM. The news keeps saying “another memory maker’s HBM is sold out,” but what exactly is HBM, why can’t a GPU live without it, and how does it differ from the memory stick in your computer?
This piece lays HBM out in plain terms all at once. First what it is and how it differs from ordinary memory, then why AI can’t do without it, how the three-way oligopoly plays out, and why HBM4 is the new battleground of 2026. This is the deep-dive version of Gate 2 in The AI Hardware Supply Chain, End to End.
What Is HBM? One Sentence and One Picture
HBM stands for High Bandwidth Memory. What it does is take several layers of DRAM memory dies and stack them vertically, connect them top-to-bottom with through-silicon vias (TSVs — essentially vertical channels drilled through the chip), and then hug the GPU through an extremely wide interface (the data channel between GPU and memory).
Here’s the picture. The memory in an ordinary computer lies flat, slotted one stick at a time onto the motherboard. HBM instead stands the memory up and stacks it layer upon layer, then moves it almost flush against the GPU. So the easiest way to remember it: HBM is “ultra-wide memory that stands up,” built so the GPU never starves waiting for data.
Why stack it and put it so close? Because the volume of data an AI chip has to swallow every second is staggering. Flat traditional memory, with an interface that isn’t wide enough and a distance that’s too far, simply can’t feed it fast enough. Stack the memory tall, widen the interface, shorten the distance, and bandwidth can leap to several terabytes per second in one go. The cost is that it has to use advanced packaging like CoWoS (the technology that puts the GPU and HBM into the same high-end package) to bond with the GPU, so manufacturing difficulty and cost both run high.
How It Differs From Ordinary Memory (DDR)
A lot of people ask: so is HBM going to replace the memory in my computer? No. They serve different scenarios.
Ordinary DDR memory is general-purpose system memory — cheap, easy to expand, the thing that runs your OS, opens web pages, and plays games, like a well-connected ordinary road. HBM is a specialty part purpose-built for AI and high-performance computing — expensive, hard to make, limited in capacity, like an ultra-wide highway bolted right next to the GPU. Its real strengths are width and distance: an absurd number of lanes and an extremely short trip to the destination.
So these two kinds of memory coexist. Your laptop won’t use HBM, and the GPU in an AI server won’t rely on DDR alone. Grasp this and you won’t conflate “memory shortage” with “HBM shortage.” As we’ll see, what really jams up AI is HBM, this specialty highway.
Why AI Chips Can’t Do Without HBM
Think of the GPU as a monster engine. No matter how fierce the engine, too thin a fuel line and it still won’t run. For an AI chip, that fuel line is memory bandwidth.
During training and inference, AI constantly moves model weights and intermediate results into the compute cores. The moment memory can’t feed data fast enough, thousands of compute cores stall in “idle waiting,” and even the most expensive compute power is wasted. HBM exists to make that fuel line thick enough, so the GPU’s cores always have data to chew on.
That’s why flagship AI chips routinely strap on several HBM stacks. In one line: HBM is the fuel line of the AI accelerator — without enough bandwidth, even the strongest engine can’t get fed.
Core-Data Snapshot
Below are the key numbers for understanding the HBM contest. To be clear up front, market-share figures like these are research-firm estimates that shift quarter by quarter, so read them for order of magnitude and trend rather than chasing the decimal point.
| Topic | Data | Time / Nature |
|---|---|---|
| HBM revenue market share | SK Hynix ~57%, Samsung ~22%, Micron ~21% | 2025 Q3, Counterpoint estimate |
| HBM3e specs (Micron) | 1024-bit interface, over 9.2 Gb/s per pin, over 1.2 TB/s per stack; 8-high 24GB, 12-high 36GB | 2025-2026 mass production |
| HBM4 standard (JEDEC) | 2048-bit interface, up to 8 Gb/s per pin, up to 2 TB/s per stack; standard supports taller stacks and higher capacity | Released 2025-04 |
| HBM4 actual products | Micron 36GB / 12-high, over 2.8 TB/s; Samsung 11.7-13 Gb/s per pin, up to 3.3 TB/s (48GB / 16-high still sampling or planned) | Mass production from 2026 Q1 |
| Supply status | Demand far exceeds supply; industry warns shortages could last until 2027 and beyond | 2026, multiple reports |
The Three-Way Oligopoly
HBM is a textbook three-horse race with an extremely high barrier — new players can barely get in.
SK Hynix has long led, with over half the market and the edge in both technology and yield; even the latest HBM4 was the first it finished developing and readied for mass production (second half of 2025, breaking past 10 Gb per second). Samsung fell behind for a stretch in the HBM3 generation, then announced HBM4 mass production in early 2026 and started commercial shipments, catching up. Micron has charged hardest these past two years, lifting its share from single digits to roughly 20%, and in the first quarter of 2026 mass-produced HBM4 clearly matched to Nvidia’s next-generation Vera Rubin platform.
What’s worth noting is the rhythm of this fight: whoever first gets the latest-generation HBM into mass production AND through Nvidia certification gets the biggest slice of the next round of orders. So the three aren’t just competing on “can you make it,” but on “who’s first, how high the yield, and how much can you supply.”
How HBM3e and HBM4 Differ, and What Comes Next
Each HBM generation mainly competes on three things: how wide the interface, how tall a single stack can go, and how fast it runs.
What’s shipping in volume today is HBM3e, with a 1024-bit interface and per-stack bandwidth already past 1.2 TB per second. The new-generation HBM4 was finalized by JEDEC in April 2025, and the biggest change is widening the interface from 1024-bit straight to 2048-bit — doubling the highway’s lanes. The actual products outdo the standard: Micron’s and Samsung’s HBM4 both reach per-stack bandwidth in the 2.8-to-3.3 TB-per-second class.
The battlefield further ahead is already lining up. At Nvidia’s 2026 GTC conference (Nvidia’s annual developer conference), Samsung showed off a faster HBM4E, claiming 16 Gb/s per pin and 4.0 TB/s per stack, and previewed that custom HBM would sample in 2027. Simply put, HBM4 has only just entered mass production, and the race for the next generation and custom versions is already on.
Why Supply Stays So Tight
The HBM shortage isn’t just about hot demand — the real trouble is that ramping capacity is inherently slow, with structural reasons behind it.
Its process is complex, yield is hard to lift, and it has to pair with CoWoS advanced packaging, so capacity expansion is inherently slower than AI’s appetite. The result: long-term contracts lock supply down. Per earnings-call coverage, Micron’s 2026 HBM output is largely already booked by customers under long-term contracts; Samsung and SK Hynix have publicly warned that AI-driven memory shortages could last until 2027 or even longer, with customers already reserving volume years out.
The supply-demand gap also shows up in price. Research firm TrendForce estimates HBM4 unit prices run more than 30% above HBM3e; if suppliers ramp smoothly, HBM4 could overtake HBM3e as the mainstream in the second half of 2026 — but that’s a projection, and HBM3e still ships in volume in 2026. For the whole AI supply chain, this means that even if GPU and packaging capacity expand, as long as HBM can’t keep up, the full system still can’t ship.
Taiwan’s Role at This Gate
First, a common misconception: Taiwan has no domestically mass-produced HBM brand. HBM wafers are mainly held by South Korea’s SK Hynix and Samsung, and the U.S.’s Micron (Micron has DRAM/HBM-related manufacturing and expansion in Taiwan, but the HBM brand and product responsibility still belong to Micron, not a Taiwanese brand). So looking purely at “who makes HBM,” Taiwan isn’t the lead.
But pull the lens to the downstream and it changes. For HBM to do its job, it has to rely on advanced packaging like CoWoS to hug the GPU, and that gate is highly concentrated in Taiwan. The scarcer and pricier HBM gets, the more the bargaining power of advanced packaging and system integration is amplified. Add in the server contract manufacturing for Nvidia’s next-generation platform, where nearly everyone named is a Taiwanese firm. So at the HBM gate, Taiwan’s role lands in the key downstream links of packaging, testing, and server integration, and gets pulled directly by AI accelerator demand.
Key Takeaways
After looking at HBM, a few things are worth remembering.
HBM is “ultra-wide memory that stands up,” serving as the fuel line for the AI accelerator. Without enough bandwidth, even the strongest GPU can’t get fed, which makes it a key part — alongside advanced packaging — that jams up the entire AI supply chain.
It’s an oligopoly of SK Hynix, Samsung, and Micron, with demand outstripping supply into 2027 and beyond and prices still climbing. The latest HBM4 entered mass production in 2026, with Micron’s most clearly matched to Nvidia’s Vera Rubin platform, while the next round of competition over HBM4E and custom HBM has already begun.
To read on about the advanced packaging that binds HBM and GPU into one piece, see What Is CoWoS; to see how all eight gates of the chain string together, head back to the supply-chain overview.